Circuits and systems that utilize analog-to-digital converters (ADCs) may increase bandwidth without an appreciable increase in power consumption by using time-interleaved ADCs. A typical time-interleaved ADC circuit includes a plurality of ADC channels each configured to sample an analog input signal to generate a corresponding digital output signal. The digital output signals provided by the ADC channels may be combined to generate a combined output signal having a sampling bandwidth equal to an integer multiple of the sampling bandwidth of the individual ADC channels. For example, a time-interleaved ADC circuit that includes a number N of ADC channels may generate a digital output signal having a sampling bandwidth (fBW) equal to N times the sampling bandwidth (fs) of the individual ADC channels (such that fBW=N*fs).
Time-skew mismatches, gain mismatches, frequency offsets, and phase offsets between the individual channels of a time-interleaved ADC circuit may adversely affect performance of the time-interleaved ADC circuit. Calibration circuits may be used to compensate for these mismatches and offsets between the individual ADC channels.